Is this product dead?

General Topics about DSLogic project
Anders wrote:(I've pushed that fix, and a couple of other minor patches to my github fork: )

Thanks for that.

I keep working in the trigger, and it seems that at least the falling trigger works now. (but only the falling trigger, regardless of the choosen trigger :(... also pre-trigger samples dont work).

Anyway, I pushed a new branch (named trigger ) in the repository.

Posts: 6
Joined: Wed Jan 21, 2015 5:51 am


Today I've spent few hours to look at the DSlogic project.
My initial goal is to optimize the memory utilization, for example If user selects 2 channels he gets 8 times longer record in comparison all 16 signals are enabled. I brawsed all PC software/firmware and HDL code and I made some notes to help me later when I found time for this project.
Though not tidy I think notescould be usefull for others:

Some conventions:
'PC' is where DSlogic GUI is executed
'CPU' is Cypress micro controller, 'firmware' is running on it

DSLogic ================================================
-command_fpga_setting() DSLogic is sending special command to the CPU that it is about to send FPGA settings.
As argument it sends 3 bytes specifying the count of the settings data

-fpga_setting() prepares DSLogic_setting structure and sends it to the HDL layer. It uses libusb_bulk_transfer()

-fpga_config() sends data to the CPU for reprogramming of the FPGA bit-stream. It uses libusb_bulk_transfer()

DSLogic fw ==============================================
-fx2lib library is used by the firmware layer, USB End Point 2 (out), End Point 6 (in)

-GPIF is a flexible hardware GPIO state machine having control outputs, checking few control inputs for a given condition before proceeding to the next state
GPIF is able to set address bus and reading/writing from/to data bus. Settings of the GPIF operation is configure by const char WaveData[128] array
CPU uses GPIF interface to talk to the FPGA.
For example gpif_fifo_read(GPIF_EP6) is used to read the logic analyzed captured data.

- handle_vendorcommand() hook for the command byte, it assign the command variable with the command sent by the GUI

- main CPU loop looks like

- after getting CMD_SETTING command the CPU is reading the 3 data count bytes and configures the GPIF system to output the data from EP2 to the FPGA

- To write the FPGA settings (comming from EP2) the CPU is using GPIF interface

FPGA/HDL ==============================================
FIFO interface is a 16 bit parallel interface which is connected to the CPU GPIF, here DreamsourceLab calls it USB interface
In the released HDL code there is not direct correspondence between the FIFO interface signal names and the schematics.
Following substitution needs to be done, rest of the FIFO signals on the schematics are not used
usb_data[0..15] -> FIFO[0..15] (SCH)
usb_overflow -> FIFO_ADDR0(SCH)
usb_rdy -> FPGA_INIT_B(SCH)
usb_rdwr -> FPGA_RDWR_B(SCH)
usb_en -> FPGA_CSI_B(SCH)

The mapping "struct DSLogic_setting" and the HDL registers file (inside FPGA) is defined in /DSLogic-hdl/src/cfg.v
The comments in the code below specifies the config register index in the HDL description.

struct DSLogic_setting {
uint32_t sync;
uint16_t mode_header; // 0
uint16_t mode;
uint32_t divider_header; // 1-2
uint32_t divider;
uint32_t count_header; // 3-4
uint32_t count;
uint32_t trig_pos_header; // 5-6
uint32_t trig_pos;
uint16_t trig_glb_header; // 7
uint16_t trig_glb;
uint32_t trig_adp_header; // 10-11
uint32_t trig_adp;
uint32_t trig_sda_header; // 12-13
uint32_t trig_sda;
uint32_t trig_mask0_header; // 16
uint16_t trig_mask0[NUM_TRIGGER_STAGES];
uint32_t trig_mask1_header; // 17
uint16_t trig_mask1[NUM_TRIGGER_STAGES];
//uint32_t trig_mask2_header; // 18
//uint16_t trig_mask2[NUM_TRIGGER_STAGES];
//uint32_t trig_mask3_header; // 19
//uint16_t trig_mask3[NUM_TRIGGER_STAGES];
uint32_t trig_value0_header; // 20
uint16_t trig_value0[NUM_TRIGGER_STAGES];
uint32_t trig_value1_header; // 21
uint16_t trig_value1[NUM_TRIGGER_STAGES];
//uint32_t trig_value2_header; // 22
//uint16_t trig_value2[NUM_TRIGGER_STAGES];
//uint32_t trig_value3_header; // 23
//uint16_t trig_value3[NUM_TRIGGER_STAGES];
uint32_t trig_edge0_header; // 24
uint16_t trig_edge0[NUM_TRIGGER_STAGES];
uint32_t trig_edge1_header; // 25
uint16_t trig_edge1[NUM_TRIGGER_STAGES];
//uint32_t trig_edge2_header; // 26
//uint16_t trig_edge2[NUM_TRIGGER_STAGES];
//uint32_t trig_edge3_header; // 27
//uint16_t trig_edge3[NUM_TRIGGER_STAGES];
uint32_t trig_count0_header; // 28
uint16_t trig_count0[NUM_TRIGGER_STAGES];
uint32_t trig_count1_header; // 29
uint16_t trig_count1[NUM_TRIGGER_STAGES];
//uint32_t trig_count2_header; // 30
//uint16_t trig_count2[NUM_TRIGGER_STAGES];
//uint32_t trig_count3_header; // 31
//uint16_t trig_count3[NUM_TRIGGER_STAGES];
uint32_t trig_logic0_header; // 32
uint16_t trig_logic0[NUM_TRIGGER_STAGES];
uint32_t trig_logic1_header; // 33
uint16_t trig_logic1[NUM_TRIGGER_STAGES];
//uint32_t trig_logic2_header; // 34
//uint16_t trig_logic2[NUM_TRIGGER_STAGES];
//uint32_t trig_logic3_header; // 35
//uint16_t trig_logic3[NUM_TRIGGER_STAGES];
uint32_t end_sync;

sample.v -----------------------------------------------------------------------
assign half_mode = cfg0_reg[5]; //This is for 200MHz
assign quarter_mode = cfg0_reg[6]; //This is for 400MHz

This is how port is sampled (Dual Data Rate Input D Flip-Flop)
IDDR2 ext_sync0(.Q0(pos_sync_data[0]), .Q1(neg_sync_data[0]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[0]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync1(.Q0(pos_sync_data[1]), .Q1(neg_sync_data[1]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[1]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync2(.Q0(pos_sync_data[2]), .Q1(neg_sync_data[2]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[2]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync3(.Q0(pos_sync_data[3]), .Q1(neg_sync_data[3]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[3]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync4(.Q0(pos_sync_data[4]), .Q1(neg_sync_data[4]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[4]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync5(.Q0(pos_sync_data[5]), .Q1(neg_sync_data[5]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[5]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync6(.Q0(pos_sync_data[6]), .Q1(neg_sync_data[6]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[6]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync7(.Q0(pos_sync_data[7]), .Q1(neg_sync_data[7]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[7]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync8(.Q0(pos_sync_data[8]), .Q1(neg_sync_data[8]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[8]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync9(.Q0(pos_sync_data[9]), .Q1(neg_sync_data[9]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[9]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync10(.Q0(pos_sync_data[10]), .Q1(neg_sync_data[10]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[10]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync11(.Q0(pos_sync_data[11]), .Q1(neg_sync_data[11]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[11]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync12(.Q0(pos_sync_data[12]), .Q1(neg_sync_data[12]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[12]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync13(.Q0(pos_sync_data[13]), .Q1(neg_sync_data[13]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[13]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync14(.Q0(pos_sync_data[14]), .Q1(neg_sync_data[14]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[14]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync15(.Q0(pos_sync_data[15]), .Q1(neg_sync_data[15]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[15]), .R(1'b0), .S(1'b0));

After some messy processing the data are going to asyncfifo. Seems 32 sample depth?
The output of the asyncfifo 'sample_data' is output of the sample module.

sample module also creates 'sample_valid' signal which is used to decimate the 100MHz fixed sampling to the selected by user sampling rate (50MHz, 25MHz, 20MHz, etc)
To do this DSLogic_setting.divider is used assigned in HDL variable 'sample_divider'

triger.v ------------------------------------------------------------------------
This module takes lot of input arguments and the sample_data and produces 'trig_hit' output

capture.v ---------------------------------------------------------------------
This module takes 'trig_hit' and 'sample_data' and produce 'capture_data'

dwrite.v -----------------------------------------------------------------------
The 'capture_data' is buffered in async fifo
async fifo / core_clk -> sdram_clk

mem_ctrl.v -----------------
captured data stored in SDRAM using mem_ctrl module.
this module is used also to read the data in sd_rd_data

dread.v ----------------------
again async fifo and data are read using mem_ctrl
and are read by the CPU

The FPGA gets it clock from IFCLK output of the CPU (30Mhz in our case) and is called cclk
PLL is used which produce the following clocks.
Multiplication and division factors are set for each clock in ./ipcore_dir/core_dcm.v

// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
// usb_clk ______30.000______0.000______50.0______380.769____232.277
// core_clk _____100.001______0.000______50.0______284.057____232.277
// int_clk _______100.001____315.000______50.0______284.057____232.277
// int_clk_2x ____200.002____315.000______50.0______239.188____232.277
// out_clk ______100.001______0.000______50.0______284.057____232.277

-sample_clk is either 100 or 200MHz (if user selects 400MHz sampling rate)

-But in case of 400MHz sampling rate only even samples are stored in asynfifo (sample.v)

-In addition sampling process accepts a change in a signal only if two consecutive equal samples are got.
If two consecutive and diferent samples are observed then sampler just produce the previous value.

-As a result in DSLogic we basicly have maximum 100MHz sampling process.
Sampler outputs:
-In 400MHz mode => each 100MHz tick the data {0000 data[3:0] 0000 data[3:0]} , GUI shows 2 equal consecutive samples (for 4 channels) with 200Hz rate (zero data are just ignored)
-In 200MHz mode => each 100MHz tick the data {data[7:0] data[7:0]} , GUI shows 2 equal consecutive samples (for 8 channels) with 200MHz rate
-If I have interpreted the Verilog code properly 200MHz and 400Mhz rates in Dslogic are useless.
I have confirmed the above dumping some data from the DSLogic GUI software.
I have used the compiled bitstream from the released (by DreamSourceLab) DSLogic-hdl code
It is interesting that the original DSLogic33.bin (the one in bitstream has diferent behaviour
and samples are distinct (not paired ) for 200MHz

DreamSourceLab, could you please update DSLogic-hdl code in the github?

Enhancements/correcttions are welcome.

Posts: 12
Joined: Sat Dec 06, 2014 5:49 pm

Thanks dpenev, this is one of the features I asked for a few months ago!
However, I hope that the conversion to sigrok will take place. This might be more future safe!
Posts: 9
Joined: Mon Aug 18, 2014 5:42 pm

Hi electronic_n00b,

Knowing the code structure I doubt other than a very basic integration in the Sigrok could be done.
We will not be able to support more complex triggers etc.
I still thing that after some not very much efforts from a few person and we can make the DSlogic fixed and useful.

Alternatively we should find another fx2 based instrument with more clean HDL open implementation
Anyone know about such?

Posts: 12
Joined: Sat Dec 06, 2014 5:49 pm

As the status of dreamsourcelab is unknown, I would like to advise to migrate the development offsite to github for example and continue the discussions there. It could well be that this site vanishes overnight.
Posts: 6
Joined: Thu Dec 25, 2014 7:35 pm

I still wonder if Dreamsourcelab is dead or not, since there is a special offer currently running during april 2015.
It is a sign of activity, even if they are too quiet on the forum.
Posts: 5
Joined: Thu Aug 14, 2014 6:16 pm

clearout sale? aka dump it
Posts: 6
Joined: Thu Dec 25, 2014 7:35 pm

Please please start pushing your efforts of supporting DSLogic in libsigrok upstream to libsigrok so other developers can find it and contribute.
I was just lucky to find this thread that has a name "Is this product dead?" and by pure luck found that someone else was already working on the same thing I have started working on and many others on libsigrok development list.

Thanks /// Carl
Posts: 1
Joined: Wed Apr 15, 2015 3:09 pm

Really thank you all, guys.
We should say sorry for this long time without any update and news.
Now we are back, and will restart our work on this project.

We really hope to integrate all of your efforts on the old project to the new repo:

Thanks again.
Site Admin
Posts: 146
Joined: Fri Jul 11, 2014 9:20 am


for all of you that still have interest in libsigrok suport for dslogic, it is almost there!
The folks at libsigrok implemented basic support, to which I added more functionality. Check my repo for the last version:

The last working version is in branch devel.

What is working:

Simple trigger on any channel
Pre-Trigger settings
External Clock/Clock edge
Voltage Threshold.
Continuous (Stream) sampling.
Some of these changes are already on the development branch of libsigrok.

In order to use it you also need the binary firmware and the fpga image that comes with your dslogic.

Go to folder DSView/res and copy following files:

to the folder where sigrok-firmware is located (mine is in /usr/local/share/sigrok-firmware). After that rename them as follows:

DSLogic.fw -> dreamsourcelab-dslogic-fx2.fw
DSLogic33.bin -> dreamsourcelab-dslogic-fpga-3v3.fw
DSLogic50.bin -> dreamsourcelab-dslogic-fpga-5v.fw

Posts: 6
Joined: Wed Jan 21, 2015 5:51 am


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